Microprocessor-based systems are configured to operate by sequentially executing software program instructions which may be stored in consecutive memory locations. A program counter, for example, may be configured to contain a memory address of a next stored instruction in the sequence of instructions. The program counter is then incremented as each instruction is executed. The software program may include branches which are taken in accordance with the conditions specified in the program. For a conditional branch, if the condition is satisfied, a branch address may be entered in the program counter and the sequential execution of instructions resumes, beginning at the branch address.
Microprocessor-based systems, however, must respond to the occurrence of events which are not in synchronism with respect to the stored software program. For example, data from a peripheral device, such as a mouse or keyboard, should be processed immediately upon data acquisition. Accordingly, microprocessors are provided with the capability of receiving and operating in accordance with one or more interrupt signals generated by such peripheral devices, for example. In response to such interrupt signals, the microprocessor is configured to interrupt the sequential sequence of instructions being executed and instead to begin to execute a another sequential sequence of instructions, commonly referred to as an interrupt service routine, corresponding to the interrupt being serviced.
To begin executing the interrupt service routine, the address presently stored in the program counter is saved and a vector address, sometimes referred to as an interrupt vector, is inputted to and stored by the program counter. There are two alternative techniques for determining the vector address for executing the interrupt service routine. In one technique, the peripheral device causing the interrupt provides the starting address of the interrupt service routine and the starting address is inputted to and stored by the program counter of the microprocessor. The address stored in the program counter can also be an address of a location in the memory which contains the starting address of the interrupt service routine. In another technique, the vector address points to a predetermined location in the memory which is typically the starting address of a software routine referred to as an interrupt handler. The interrupt handler then initiates an interrupt service routine corresponding to the interrupt being serviced.
Upon completion of the execution of the interrupt service routine, the previously saved address is inputted to and stored by the program counter and the execution of the original sequence of instructions resumes.
When two or more interrupt signals are pending, the microprocessor must respond to these interrupt signals on a priority interrupt basis. Microprocessor-based systems accordingly are given the ability to prioritize the interrupt signals. Furthermore, if the microprocessor is performing a critical operation that cannot be interrupted, the microprocessor may be configured so as to ignore one or more interrupt signals. For this reason, microprocessors are configured to include a mechanism, referred to as processor interrupt logic, for masking interrupts based on their priority interrupt level.
The processor interrupt logic for masking interrupts based on the priority interrupt level determines the priority interrupt level of the interrupt being serviced and masks all interrupts which have the same priority interrupt level or a lower priority interrupt level than the interrupt being serviced. The processor interrupt logic for masking interrupts based on interrupt priority level is quite complicated and accordingly, a technique must be provided for testing processor interrupt logic to ensure that it is operating properly.